IO Interface
Q21.
Which of the following statements about synchronous and asynchronous I/O is NOT true?Q23.
Which of the following DMA transfer modes and interrupt handling mechanisms will enable the highest I/O band-width?Q25.
A device with data transfer rate 10 KB/sec is connected to a CPU. Data is transferred byte-wise. Let the interrupt overhead be 4 \musec. The byte transfer time between the device interfaces register and CPU or memory is negligible. What is the minimum performance gain of operating the device under interrupt mode over operating it under program-controlled mode?Q26.
Normally user programs are prevented from handling I/O directly by I/O instructions in them. For CPUs having explicit I/O instructions, such I/O protection is ensured by having the I/O instructions privileged. In a CPU with memory mapped I/O, there is no explicit I/O instruction. Which one of the following is true for a CPU with memory mapped I/O?Q28.
The correct matching for the following pairs is:\begin{array}{ll} \text{(A) DMA I/O} & \text{(1) High speed RAM} \\ \text{(B) Cache} & \text{(2) Disk} \\ \text{(C) Interrupt I/O} & \text{(3) Printer} \\ \text{(D) Condition Code Register} & \text{(4) ALU} \\ \end{array}Q29.
Consider a disk drive with the following specifications: 16 surfaces, 512 tracks/surface, 512 sectors/track, 1 KB/sector, rotation speed 3000 rpm. The disk is operated in cycle stealing mode whereby whenever one 4 byte word is ready it is sent to memory; similarly, for writing, the disk interface reads a 4 byte word from the memory in each DMA cycle. Memory cycle time is 40 nsec. The maximum percentage of time that the CPU gets blocked during DMA operation is:Q30.
What is the bit rate of a video terminal unit with 80 characters/line, 8 bits/character and horizontal sweep time of 100 \mu s (including 20 \mu s of retrace time)?